module lpuart_basic_2stage_sync#(
  parameter data_width = 1
)(
  input                   clk,
  input                   rst_n,
  input                   init_d_n,
  input  [data_width-1:0] data_s,
  output [data_width-1:0] data_d
);

reg [data_width-1:0] sample_meta;
reg [data_width-1:0] sample_syn;

always @ (posedge clk, negedge rst_n) begin
  if(!rst_n) begin
    sample_meta <= {data_width{1'b0}};
    sample_syn  <= {data_width{1'b0}};
  end else if(!init_d_n) begin
    sample_meta <= {data_width{1'b0}};
    sample_syn  <= {data_width{1'b0}};
  end else begin
    sample_meta <= data_s;
    sample_syn  <= sample_meta;
  end
end

assign data_d = sample_syn;
endmodule
